1. Field of the Invention
This invention relates to a chip on chip type integrated circuit (IC) device which comprises a plurality of chips mounted in stacked relationship and electrically interconnected, in a single IC package and, more particularly, to a circuit and related method for checking the integrity of the interconnections providing signal paths between the chips in such a chip on chip type IC device.
2. State of the Prior Art
Because of the increasing levels of integration and the corresponding, more complicated circuit functions required to be performed in IC devices, current large scale integrated (LSI) circuits often must include different types of circuits in a single package. For example, a single LSI circuit may be required to include CMOS (complimentary MOS) circuits and TTL (transistor-transistor logic) circuits, or both a CMOS digital circuit and an analog circuit. Sometime it also is required that CMOS circuits be included in an ECL (emitter coupled logic) circuit having an interface circuit. It is very difficult to provide such different kinds of circuits in a single chip, or even in those instances when such a chip can be fabricated, high production yields cannot be expected with the present state-of-the-art technology, because of the requirement that the circuit include both FET circuits and bipolar circuits in a single chip.
To satisfy these requirements in light of the difficulties of producing such single chip structures, recently there has been adopted a chip on chip type structure; particularly, such a structure attempts to satisfy the requirements as before noted, by bonding a first chip fabricated in accordance with one process sequence to another chip which is fabricated in accordance with a different process sequence, in a single package. In such structures, and even though the individual chips are tested and appropriately selected before being stacked, one on the other, the reliability of the chips as combined into a single package is not always satisfactory, because the interconnections between the chips may introduce problems. While visual inspection is effective for checking the integrity of such interconnections, including the bonding, between the chips, it is limited only to the peripheral portions of the chips which are visible and thus is inadequate.
For example, in the case of chip on chip type IC's, such as memory on logic chips or logic on logic chips, each of the individual logic circuit chip and the memory circuit chip may be checked easily and routinely, prior to being stacked and bonded together. However, it is difficult to check the chips after they have been assembled and bonded, because the upper chip is usually bonded in an upside down position on the lower chip, in facing relationship. Thus, the electric contact, or bonding, pads of the upper chip are not accessible, and therefore it is difficult to check electrically the integrity and completeness of the wiring and bonding forming the interconnections between the upper and lower chips.
The problems presented in chip on chip type IC devices, with regard to the integrity of the wiring and bonding between the stacked chips, has not been particularly serious heretofore, since the scale or level of integration was not particularly great; however, the problem is becoming increasingly serious as the scale of integration of IC devices increases and as, concomitantly, the number of bonds to complete interconnections between the chips increases.